1. Field of the Invention
The present invention relates generally to electronic circuits and systems. Specifically, the invention relates to apparatus, methods, and systems for packaging and testing integrated circuits.
2. Description of the Related Art
Semiconductor circuit technologies have experienced a steady march of process and materials improvements since their introduction in the later half of the 20th century. Such improvements have significantly decreased the geometry sizes of semiconductor devices while dramatically increasing the density, clock rates, and processing power attainable on a single chip. Despite the tremendous increase in device density achievable with semiconductors, integrated circuit packaging has limited the ability to achieve a corresponding increase in density on board level products.
To address the needs resulting from improvements in semiconductor technology, a number of changes in packaging technology have been undertaken to varying degrees of success. For example, pin grid arrays, flat packs, multi-chip modules, ball grid arrays, and flip chips have all experienced some degree of commercial success. However, many of these improvements in packaging technology have proven to be too expensive to be useful for commodity parts and circuits. One notable exception is ball grid array (BGA) packaging technology. While newer technologies exists, solder ball connections have proven to be cost-effective in that they may be placed in a dense two dimensional array resulting in small packages with high I/O capacity.
The requirements and improvements imposed upon test equipment have also increase dramatically with increased circuit density and speeds. The sheer number of devices and circuit paths involved with modern integrated circuits require the ability to independently test specific subsystems or components on a chip. Traditionally, testing and analysis of specific circuits within an integrated circuit has required additional circuitry and/or physical contact with the circuit via finely positioned probes. Such physical contact has become increasingly impractical and may damage the devices or signal paths under test.
In response to the demand for non-invasive techniques, laser interferometry has emerged as an important tool for testing and analyzing integrated circuits. Laser interferometry measures the effect of signal voltage on the phase information of a reflected beam to estimate the voltage of a particular point within an integrated circuit.
However, despite the tremendous advantage available with laser interfereometry, backside access to an integrated circuit die is required for use and most packaging technologies are currently not amenable to such access. For example, milling the bottom of a BGA package to access the backside of an integrated circuit die typically destroys circuit traces on the substrate thus limiting or preventing the use of test equipment designed for backside access.
Another challenge in packaging systems is the cost associated with designing a package for each unique integrated circuit. Each circuit may have a unique die size and I/O requirements. The time and expense involved with routing signals and bonding pads on a package substrate significantly increases the cost of introducing an integrated circuit. Particularly with application specific integrated circuits (ASICS), packaging standardization is needed in order to reduce the cost of producing custom chips.
What is needed is a standardized packaging solution that facilitates backside access and testing to a wider variety of custom integrated circuits. Specifically, what is needed is a packaging family of integrated circuit carriers that is capable of receiving a wide range of integrated circuit sizes and I/O counts with a small number of circuit carriers capable of supporting backside analysis and high density package connectors such as BGA connectors.